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c10-1. 雑誌掲載論文 >
このアイテムの引用には次の識別子を使用してください:
http://hdl.handle.net/10119/12866
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| ダブリン･コア･フィールド | 値 | 言語 |
|---|
| contributor.author | Dao, Toan Thanh | en_US |
| contributor.author | Murata, Hideyuki | en_US |
| date.accessioned | 2015-07-30T08:12:45Z | - |
| date.available | 2015-07-30T08:12:45Z | - |
| date.issued | 2015-05-01 | en_US |
| identifier.uri | http://hdl.handle.net/10119/12866 | - |
| description.abstract | We have demonstrated tunable n-channel fullerene and p-channel pentacene OFETs and CMOS inverter circuit based on a bilayer-dielectric structure of CYTOP (poly(perfluoroalkenyl vinyl ether)) electret and SiO_2. For both OFET types, the V_<th> can be electrically tuned thanks to the charge-trapping at the interface of CYTOP and SiO_2. The stability of the shifted V_<th> was investigated through monitoring a change in transistor current. The measured transistor current versus time after programming fitted very well with a stretched-exponential distribution with a long time constant up to 10^6 s. For organic CMOS inverter, after applying the program gate voltages for n-channel fullerene or p-channel pentacene elements, the voltage transfer characteristics were shifted toward more positive values, resulting in a modulation of the noise margin. We realized that at a program gate voltage of 60 V for p-channel OFET, the circuit switched at 4, 8 V, that is close to half supply voltage V_<DD>, leading to the maximum electrical noise immunity of the inverter circuit. | en_US |
| format.extent | 1124273 bytes | - |
| format.mimetype | application/pdf | - |
| language.iso | en | en_US |
| publisher | 電子情報通信学会 | en_US |
| rights | Copyright (C)2015 IEICE. Toan Thanh Dao and Hideyuki Murata, IEICE TRANSACTIONS on Electronics, E98-C(5), 2015, 422-428. http://www.ieice.org/jpn/trans_online/ | en_US |
| subject | controllable threshold voltage | en_US |
| subject | stretch-exponential equation | en_US |
| subject | noise margin enhancement | en_US |
| subject | organic CMOS inverter | en_US |
| title | Tunable Threshold Voltage of Organic CMOS Inverter Circuits by Electron Trapping in Bilayer Gate Dielectrics | en_US |
| type.nii | Journal Article | en_US |
| identifier.niiissn | 0916-8524 | en_US |
| identifier.jtitle | IEICE TRANSACTIONS on Electronics | en_US |
| identifier.volume | E98-C | en_US |
| identifier.issue | 5 | en_US |
| identifier.spage | 422 | en_US |
| identifier.epage | 428 | en_US |
| relation.doi | 10.1587/transele.E98.C.422 | en_US |
| rights.textversion | publisher | en_US |
| language.iso639-2 | eng | en_US |
| 出現コレクション: | c10-1. 雑誌掲載論文 (Journal Articles)
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このアイテムのファイル:
| ファイル |
記述 |
サイズ | 形式 |
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| 21450.pdf | | 1097Kb | Adobe PDF | 見る/開く |
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