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Please use this identifier to cite or link to this item: http://hdl.handle.net/10119/15464

Title: A Study of Reducing Jitter and Energy Consumption in Hard Real-Time Systems using Intra-task DVFS Techniques
Authors: Tseng, Bo-Yu
Authors(alternative): ぜん, ぼーゆー
Keywords: finish time jitter
Dynamic Voltage and Frequency Scaling
Control and Data Flow Analysis
worst-case interference time
worst-case execution time
response time
Issue Date: Sep-2018
Description: Supervisor:田中 清史
先端科学技術研究科
修士(情報科学)
Title(English): A Study of Reducing Jitter and Energy Consumption in Hard Real-Time Systems using Intra-task DVFS Techniques
Authors(English): Tseng, Bo-Yu
Language: eng
URI: http://hdl.handle.net/10119/15464
Appears in Collections:M-IS. 平成30年度 (Jun.2018 - Mar.2019)

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