JAIST Repository >
JAIST >
Theses >
Master of Science(Information Science) >
R02) (Jun.2020 - Mar.2021 >

Please use this identifier to cite or link to this item: http://hdl.handle.net/10119/16859

Title: Accelerating bit-based finite automaton on a GPGPU device
Authors: Vu, Kien Chi
Authors(alternative): ぶ, きえん ち 
Keywords: Packet filtering
regular expression
parallel processing
GPGPU
Issue Date: Sep-2020
Description: Supervisor:井口 寧
Graduate School of Advanced Science and Technology
Master of Science (Information Science)
Title(English): Accelerating bit-based finite automaton on a GPGPU device
Authors(English): Vu, Kien Chi
Language: eng
URI: http://hdl.handle.net/10119/16859
Appears in Collections:M-IS. 2020年度(R02) (Jun.2020 - Mar.2021)

Files in This Item:

File Description SizeFormat
abstract.pdf34KbAdobe PDFView/Open
paper.pdf2254KbAdobe PDFView/Open

All items in DSpace are protected by copyright, with all rights reserved.

 


Contact : Library Information Section, Japan Advanced Institute of Science and Technology