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このアイテムの引用には次の識別子を使用してください:
http://hdl.handle.net/10119/12155
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| タイトル: | An analog VLSI implementation of one-class support vector machine for multiclass classification of highly dimensional vectors |
| 著者: | Zhang, Renyuan
Kaneko, Mineo
Shibata, Tadashi |
| 発行日: | 2014-02-28 |
| 出版者: | IOP Publishing |
| 誌名: | Japanese Journal of Applied Physics |
| 巻: | 53 |
| 号: | 4S |
| 開始ページ: | 04EE03-1 |
| 終了ページ: | 04EE03-8 |
| DOI: | 10.7567/JJAP.53.04EE03 |
| 抄録: | A one-class support vector machine (OC-SVM) is implemented using an on-chip-trainable analog VLSI processor. The one-class classification of highly dimensional sample vectors can be solved with this analog processor. Since the OC-SVM learning mechanism is complicated, a special solution scheme for the learning operation is proposed on the basis of analog computational circuitries and a fully parallel architecture. In this manner, the built VLSI processor achieves a high learning speed and a compact chip area at the same time. By combining multiple OC-SVM processors, multiclass recognition can be implemented with an arbitrary number of classes. The proof-of-concept chip is fabricated for the recognition of 64-dimensional vectors representing real image patterns. Three OC-SVM processors are combined for three classes of samples, where all the on-chip learning operations are accomplished within 0.6 µs. From the measurement results, all the test patterns are correctly recognized or rejected by the recognition system built. |
| Rights: | This is the author's version of the work. It is posted here by permission of The Japan Society of Applied Physics. Copyright (C) 2014 The Japan Society of Applied Physics. Renyuan Zhang, Mineo Kaneko and Tadashi Shibata, Japanese Journal of Applied Physics, 53(4S), 2014, 04EE03-1-04EE03-8. http://dx.doi.org/10.7567/JJAP.53.04EE03 |
| URI: | http://hdl.handle.net/10119/12155 |
| 資料タイプ: | author |
| 出現コレクション: | b10-1. 雑誌掲載論文 (Journal Articles)
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このアイテムのファイル:
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記述 |
サイズ | 形式 |
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| 20270.pdf | | 2803Kb | Adobe PDF | 見る/開く |
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