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このアイテムの引用には次の識別子を使用してください:
http://hdl.handle.net/10119/16140
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| ダブリン･コア･フィールド | 値 | 言語 |
|---|
| contributor.author | Yamaguchi, Seira | en_US |
| contributor.author | Ohdaira, Keisuke | en_US |
| date.accessioned | 2019-11-05T01:07:54Z | - |
| date.available | 2019-11-05T01:07:54Z | - |
| date.issued | 2017-07-13 | en_US |
| identifier.uri | http://hdl.handle.net/10119/16140 | - |
| description.abstract | The degradation behavior of crystalline silicon (c-Si) solar cells in a cell-level potential-induced degradation (PID) test and the effect of the test conditions are reported. The PID tests were performed in a vacuum chamber by applying a voltage of 1000 V from a temperature-controlled aluminum chuck underneath an unlaminated sample stack to the top copper electrode placed on the stack. The stack was composed of soda-lime glass, an ethylene vinyl-acetate copolymer sheet, and a conventional p-type c-Si solar cell. The investigated solar cell exhibited a large degradation of the fill factor and slight degradation of the open-circuit voltage. These degradations were mainly caused by a reduction in the parallel resistance, which is the same degradation behavior as that reported previously. This indicates that the cell-level PID test well reproduces the typical degradation behavior. However, the leakage current in the unlaminated sample stack at a relatively low temperature exhibited a different temperature dependence from that in a laminated sample stack. The difference in the temperature dependence was caused by temperature-dependent contact resistances within the unlaminated sample stacks. This indicates that there is a difference between the temperature dependences in cell-level and module-level PID tests. This difference in the temperature dependence was reduced by the use of a heavier top electrode. These findings may assist in choosing the proper test conditions for this kind of cell-level PID test. A cell-level PID test for an n-type front-emitter c-Si solar cell was also performed. A typical degradation behavior, characterized by reductions in the open-circuit voltage and the short-circuit current, was observed, which implies that this test can be widely applied to PID phenomena occurring in many kinds of solar cells. | en_US |
| format.extent | 298275 bytes | - |
| format.mimetype | application/pdf | - |
| language.iso | en | en_US |
| publisher | Elsevier | en_US |
| rights | Copyright (C)2017, Elsevier. Licensed under the Creative Commons Attribution-NonCommercial-NoDerivatives 4.0 International license (CC BY-NC-ND 4.0). [http://creativecommons.org/licenses/by-nc-nd/4.0/] NOTICE: This is the author’s version of a work accepted for publication by Elsevier. Changes resulting from the publishing process, including peer review, editing, corrections, structural formatting and other quality control mechanisms, may not be reflected in this document. Changes may have been made to this work since it was submitted for publication. A definitive version was subsequently published in Seira Yamaguchi, Keisuke Ohdaira, Solar Energy, 155, 2017, 739-744, http://dx.doi.org/10.1016/j.solener.2017.07.009 | en_US |
| subject | Potential-induced degradation | en_US |
| subject | Reliability test | en_US |
| subject | Crystalline silicon solar cell | en_US |
| subject | Leakage current | en_US |
| title | Degradation behavior of crystalline silicon solar cells in a cell-level potential-induced degradation test | en_US |
| type.nii | Journal Article | en_US |
| identifier.niiissn | 0038-092X | en_US |
| identifier.jtitle | Solar Energy | en_US |
| identifier.volume | 155 | en_US |
| identifier.spage | 739 | en_US |
| identifier.epage | 744 | en_US |
| relation.doi | 10.1016/j.solener.2017.07.009 | en_US |
| rights.textversion | author | en_US |
| language.iso639-2 | eng | en_US |
| 出現コレクション: | c10-1. 雑誌掲載論文 (Journal Articles)
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このアイテムのファイル:
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| 3026.pdf | | 291Kb | Adobe PDF | 見る/開く |
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