JAIST Repository >
School of Information Science >
Articles >
Journal Articles >

Please use this identifier to cite or link to this item: http://hdl.handle.net/10119/4676

Title: A Systolic Array RLS Processor
Authors: ASAI, Takahiro
MATSUMOTO, Tadashi
Keywords: RLS algorithm
channel estimation
QR decomposition
parallel pipelined processing
ASIC
Issue Date: 2001-05-01
Publisher: 電子情報通信学会
Magazine name: IEICE Transactions on Communications
Volume: E84-B
Number: 5
Start page: 1356
End page: 1361
Abstract: This paper presents the outline of the systolic array recursive least-squares (RLS) processor prototyped primarily with the aim of broadband mobile communication applications. To execute the RLS algorithm effectively, this processor uses an orthogonal triangularization technique known in matrix algebra as QR decomposition for parallel pipelined processing. The processor board comprises 19 application-specific integrated circuit chips, each with approximately one million gates. Thirty-two bit fixed-point signal processing takes place in the processor, with which one cycle of internal cell signal processing requires approximately 500 nsec, and boundary cell signal processing requires approximately 80 nsec. The processor board can estimate up to 10 parameters. It takes approximately 35 μs to estimate 10 parameters using 41 known symbols. To evaluate signal processing performance of the prototyped systolic array processor board, processing time required to estimate a certain number of parameters using the prototyped board was comapred with using a digital signal processing (DSP) board. The DSP board performed a standard form of the RLS algorithm. Additionally, we conducted minimum mean-squared error adaptive array in-lab experiments using a complex baseband fading/array response simulator. In terms of parameter estimation accuracy, the processor is found to produce virtually the same results as a conventional software engine using floating-point operations.
Rights: Copyright (C)2001 IEICE. T. Asai and T. Matsumoto, IEICE Transactions on Communications, E84-B(5), 2001, 1356-1361. http://www.ieice.org/jpn/trans_online/
URI: http://hdl.handle.net/10119/4676
Material Type: publisher
Appears in Collections:b10-1. 雑誌掲載論文 (Journal Articles)

Files in This Item:

File Description SizeFormat
9949.pdf760KbAdobe PDFView/Open

All items in DSpace are protected by copyright, with all rights reserved.

 


Contact : Library Information Section, Japan Advanced Institute of Science and Technology