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このアイテムの引用には次の識別子を使用してください: http://hdl.handle.net/10119/5005

タイトル: A 1K-Gate GaAs Gate Array
著者: Ikawa, Yasuo
Toyoda, Nobuyuki
Mochizuki, Masao
Terada, Toshiyuki
Kanazawa, Katsue
Hirose, Mayumi
Mizoguchi, Takamaro
Hojo, Akimichi
発行日: 1984-10
出版者: Institute of Electrical and Electronics Engineers (IEEE)
誌名: IEEE Journal of Solid-State Circuits
巻: 19
号: 5
開始ページ: 721
終了ページ: 728
抄録: 1050-gate arrays have been successfully designed and fabricated. Chip size is 3.75×3.75 mm. A basic cell can be programmed as an E/D-type DCFL three-input NOR gate. Speed performance measured at 0.2-mW/gate power dissipation was as follows. Unloaded (fanout=1) propagation delay time was 100 ps/gate. Load dependence of the delay time was 65 ps/1 mm interconnection line, 27 ps/fanout, and 3.33 ps/crossover load. This leads to 350 ps/gate delay under the assumed loading condition of interconnection line length=3 mm and three fanouts. The gate array was applied to 6×6 bit parallel multiplier circuit. The 10.6 ns multiplication time was measured at 380 mW power consumption. The operation speed of the personalized circuit can be well described by the basic performance provided by ring oscillator measurement.
Rights: Copyright (C)1984 IEEE. Reprinted from IEEE Journal of Solid-State Circuits, 19(5), 1984, 721-728. This material is posted here with permission of the IEEE. Such permission of the IEEE does not in any way imply IEEE endorsement of any of JAIST's products or services. Internal or personal use of this material is permitted. However, permission to reprint/republish this material for advertising or promotional purposes or for creating new collective works for resale or redistribution must be obtained from the IEEE by writing to pubs-permissions@ieee.org. By choosing to view this document, you agree to all provisions of the copyright laws protecting it.
URI: http://hdl.handle.net/10119/5005
資料タイプ: publisher
出現コレクション:a10-1. 雑誌掲載論文 (Journal Articles)


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