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このアイテムの引用には次の識別子を使用してください: http://hdl.handle.net/10119/8369

タイトル: Shifted Recursive Torus interconnection network for massively parallel computers
著者: Inoguchi, Yasushi
Horiguchi, Susumu
発行日: 1996-03-15
出版者: 北陸先端科学技術大学院大学情報科学研究科
誌名: Research report (School of Information Science, Japan Advanced Institute of Science and Technology)
巻: IS-RR-96-0008A
開始ページ: 1
終了ページ: 19
抄録: A number of interconnection networks have been proposed for multiprocessor systems from view points of theoretical and industrial interests. In order to construct massively parallel computers in VLSI implementation, interconnection between processing elements is one of the critical problems. The number of links between processing elements are limited to reduce wiring area. On the other side, Scale Integration (WSI) has been attracted as a technology to implement a number of PEs on a silicon wafer. So defect and fault-tolerance schemes are also very important for massively parallel computers. In this paper, we propose Shifted Recursive Torus (SRT) interconnection network based on shifting torus network to build multi-level interconnection recursively. The SRT interconnection network is designed by taking account of the limited number of links, easy implementation in VLSI and hierarchical structure for expandability. The SRT is defined as one dimensional interconnection network and is extended into two dimensional interconnection network. Network features such as diameter and average distance of SRT are discussed in detail. A reconfiguration strategy of the SRT proposed as a defect-tolerance scheme.
URI: http://hdl.handle.net/10119/8369
資料タイプ: publisher
出現コレクション:IS-RR-1996

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