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このアイテムの引用には次の識別子を使用してください: http://hdl.handle.net/10119/5008

タイトル: A 6K-Gate GaAs Gate Array with a New Large-Noise-Margin SLCF Circuit
著者: Terada, Toshiyuki
Ikawa, Yasuo
Kameyama, Atsushi
Kawakyu, Katsue
Sasaki, Tadahiro
Kitaura, Yoshiaki
Ishida, Kenji
Nishihori, Kazuya
Toyoda, Nobuyuki
発行日: 1987-10
出版者: Institute of Electrical and Electronics Engineers (IEEE)
誌名: IEEE Journal of Solid-State Circuits
巻: 22
号: 5
開始ページ: 755
終了ページ: 761
抄録: A 6K-gate GaAs gate array has been successfully designed and fabricated using a new large-noise-margin Schottky-diode level-shifter capacitor-coupled FET logic (SLCF) circuitry and a WN_x-gate self-aligned LDD structure GaAs MESFET process. Chip size was 8.0×8.0 mm^2. A basic cell can be programmed as an SLCF inverter, a two-input NOR, or a two-input NAND gate. The unloaded propagation delay time was 76 ps/gate at a 1.2-mW/gate power dissipation. The increases in delay time due to various loading capacitances were 10 ps/fan-in, 45 ps/fan-out, and 0.64 ps/fF. A 16-bit serial-to-parallel-to-serial (S/P/S) data-conversion circuit was constructed on the gate array as an application example. A maximum operation frequency of 852 MHz was achieved at a 952-mW power dissipation, including I/O buffers.
Rights: Copyright (C)1987 IEEE. Reprinted from IEEE Journal of Solid-State Circuits, 22(5), 1987, 755-761. This material is posted here with permission of the IEEE. Such permission of the IEEE does not in any way imply IEEE endorsement of any of JAIST's products or services. Internal or personal use of this material is permitted. However, permission to reprint/republish this material for advertising or promotional purposes or for creating new collective works for resale or redistribution must be obtained from the IEEE by writing to pubs-permissions@ieee.org. By choosing to view this document, you agree to all provisions of the copyright laws protecting it.
URI: http://hdl.handle.net/10119/5008
資料タイプ: publisher
出現コレクション:a10-1. 雑誌掲載論文 (Journal Articles)

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