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このアイテムの引用には次の識別子を使用してください:
http://hdl.handle.net/10119/8518
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| タイトル: | Simultaneous Optimization of Skew and Control Step Assignments in RT-Datapath Synthesis |
| 著者: | OBATA, Takayuki
KANEKO, Mineo |
| キーワード: | high level synthesis
RT datapath
skew
wiring delay
scheduling |
| 発行日: | 2008-12-01 |
| 出版者: | 電子情報通信学会 |
| 誌名: | IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences |
| 巻: | E91-A |
| 号: | 12 |
| 開始ページ: | 3585 |
| 終了ページ: | 3595 |
| DOI: | 10.1093/ietfec/e91-a.12.3585 |
| 抄録: | As well as the schedule affects system performance, the control skew, i.e., the arrival time difference of control signals between registers, can be utilized for improving the system performance, enhancing robustness against delay variations, etc. The simultaneous optimization of the control step assignment and the control skew assignment is more powerful technique in improving performance. In this paper, firstly, we prove that, even if the execution sequence of operations which are assigned to the same resource is fixed, the simultaneous optimization problem under a fixed clock period is NP-hard. Secondly, we propose a heuristic algorithm for the simultaneous control step and skew optimization under given clock period, and we show how much the simultaneous optimization improves system performance. This paper is the first one that uses the intentional skew to shorten control steps under a specified clock period. The proposed algorithm has the potential to play a central role in various scenarios of skew-aware high level synthesis. |
| Rights: | Copyright (C)2008 IEICE. Takayuki OBATA, Mineo KANEKO, IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences, E91-A(12), 2008, 3585-3595. http://www.ieice.org/jpn/trans_online/ |
| URI: | http://hdl.handle.net/10119/8518 |
| 資料タイプ: | publisher |
| 出現コレクション: | b10-1. 雑誌掲載論文 (Journal Articles)
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このアイテムのファイル:
| ファイル |
記述 |
サイズ | 形式 |
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| 14055.pdf | | 394Kb | Adobe PDF | 見る/開く |
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