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このアイテムの引用には次の識別子を使用してください:
http://hdl.handle.net/10119/4656
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| タイトル: | Efficient Constraint Extraction for Template-Based Processor Self-Test Generation |
| 著者: | Kambe, Kazuko
Iwagaki, Tsuyoshi
Inoue, Michiko
Fujiwara, Hideo |
| 発行日: | 2005-12 |
| 出版者: | Institute of Electrical and Electronics Engineers (IEEE) |
| 誌名: | Proceedings. 14th Asian Test Symposium, 2005. |
| 開始ページ: | 444 |
| 終了ページ: | 449 |
| DOI: | 10.1109/ATS.2005.52 |
| 抄録: | This paper presents efficient method to extract constraints from a test program template and synthesize a test program using constraint circuits. A test program template is an instruction sequence with unspecified operands, and represents paths for justification of test patterns and observation of test responses for a module under test (MUT). The constraint circuit represents a relation between operand values and inputs/output of the MUT, therefore it enables to obtain operand values using a standard automatic test pattern generator. Experimental results show that the proposed method generates accurate and compact constraint circuits, and we obtain high fault efficiency. |
| Rights: | Copyright (c)2005 IEEE. Reprinted from Proceedings. 14th Asian Test Symposium, 2005., 18-21 Dec. This material is posted here with permission of the IEEE. Such permission of the IEEE does not in any way imply IEEE endorsement of any of JAIST's products or services. Internal or personal use of this material is permitted. However, permission to reprint/republish this material for advertising or promotional purposes or for creating new collective works for resale or redistribution must be obtained from the IEEE by writing to pubs-permissions@ieee.org. By choosing to view this document, you agree to all provisions of the copyright laws protecting it. |
| URI: | http://hdl.handle.net/10119/4656 |
| 資料タイプ: | publisher |
| 出現コレクション: | b11-1. 会議発表論文・発表資料 (Conference Papers)
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このアイテムのファイル:
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記述 |
サイズ | 形式 |
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| 5378.pdf | | 166Kb | Adobe PDF | 見る/開く |
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