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このアイテムの引用には次の識別子を使用してください:
http://hdl.handle.net/10119/7797
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| タイトル: | Cache Memory Architecture for Leakage Energy Reduction |
| 著者: | Tanaka, Kiyofumi |
| 発行日: | 2007-01 |
| 出版者: | Institute of Electrical and Electronics Engineers (IEEE) |
| 誌名: | International workshop on Innovative architecture for future generation high-performance processors and systems, 2007. iwia 2007. |
| 開始ページ: | 73 |
| 終了ページ: | 80 |
| DOI: | 10.1109/IWIA.2007.12 |
| 抄録: | Recently, energy dissipation by microprocessors is getting larger, which leads to a serious problem in terms of allowable temperature and performance improvement for future microprocessors. Cache memory is effective in bridging a growing speed gap between a processor and relatively slow external main memory, and has increased in its size. Almost all of today's commercial processors, not only highperformance microprocessors but embedded ones, have onchip cache memories. However, energy dissipation in the cache memory will approach or exceed 50% of the increasing total energy dissipation by processors. An important point to note is that, in the near future, static (leakage) energy will dominate the total energy consumption in deep sub-micron processes. This paper describes cache memory architecture, especially for on-chip multiprocessors, that achieves efficient reduction of leakage energy in cache memories by exploiting gated-Vdd control, software selfinvalidation for L1 cache, and dynamic data compression for L2 cache. The simulation results show that our techniques can reduce a substantial amount of leakage energy without large performance degradation. |
| Rights: | Copyright (C) 2007 IEEE. Reprinted from International workshop on Innovative architecture for future generation high-performance processors and systems, 2007. iwia 2007. This material is posted here with permission of the IEEE. Such permission of the IEEE does not in any way imply IEEE endorsement of any of JAIST's products or services. Internal or personal use of this material is permitted. However, permission to reprint/republish this material for advertising or promotional purposes or for creating new collective works for resale or redistribution must be obtained from the IEEE by writing to pubs-permissions@ieee.org. By choosing to view this document, you agree to all provisions of the copyright laws protecting it. |
| URI: | http://hdl.handle.net/10119/7797 |
| 資料タイプ: | publisher |
| 出現コレクション: | b11-1. 会議発表論文・発表資料 (Conference Papers)
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このアイテムのファイル:
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記述 |
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| A11739.pdf | | 292Kb | Adobe PDF | 見る/開く |
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