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JAIST Repository >
著者: "IWAGAKI, Tsuyoshi"
8 著者名表示.
| 発行日 | タイトル |
著者 |
|---|
| 1-Dec-2003 | 不連続再収斂順序回路の遅延故障に対するテスト生成法 | 岩垣, 剛; 大竹, 哲史; 藤原, 秀雄; IWAGAKI, Tsuyoshi; OHTAKE, Satoshi; FUJIWARA, Hideo |
| 1-Dec-2004 | A Design Scheme for Delay Testing of Controllers Using State Transition Information | IWAGAKI, Tsuyoshi; OHTAKE, Satoshi; FUJIWARA, Hideo |
| Dec-2005 | Efficient Constraint Extraction for Template-Based Processor Self-Test Generation | Kambe, Kazuko; Iwagaki, Tsuyoshi; Inoue, Michiko; Fujiwara, Hideo |
| 1-Jun-2006 | A Low Power Deterministic Test Using Scan Chain Disable Technique | YOU, Zhiqiang; IWAGAKI, Tsuyoshi; INOUE, Michiko; FUJIWARA, Hideo |
| 1-Apr-2008 | Novel Register Sharing in Datapath for Structural Robustness against Delay Variation | INOUE, Keisuke; KANEKO, Mineo; IWAGAKI, Tsuyoshi |
| Aug-2008 | Minimizing Minimum Delay Compensations for Timing Variation-Aware Datapath Synthesis | Inoue, Keisuke; Kaneko, Mineo; Iwagaki, Tsuyoshi |
| Oct-2008 | Safe clocking register assignment in datapath synthesis | Inoue, Keisuke; Kaneko, Mineo; Iwagaki, Tsuyoshi |
| Mar-2009 | On the derivation of a minimum test set in high quality transition testing | Iwagaki, Tsuyoshi; Kaneko, Mineo |
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