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Mineo Kaneko ProfessorFaculty Profile

No.Bibliographical information
1 新世代ナノ集積回路のための多重複合型製造後調整の理論と設計 / 金子, 峰雄, 科学研究費助成事業研究成果報告書, pp.1-4, 2018-06-04
2 System design and analysis for maximum consuming power control in smart house / Umer, Saher, Kaneko, Mineo, Tan, Yasuo, Lim, Azman Osman, Journal of Automation and Control Engineering (JOACE), 2(1), pp.43-48, 2014-03, Engineering and Technology Publishing
3 An analog VLSI implementation of one-class support vector machine for multiclass classification of highly dimensional vectors / Zhang, Renyuan, Kaneko, Mineo, Shibata, Tadashi, Japanese Journal of Applied Physics, 53(4S), pp.04EE03-1-04EE03-8, 2014-02-28, The Japan Society of Applied Physics
4 Priority based maximum consuming power control in smart homes / Umer, Saher, Kaneko, Mineo, Tan, Yasuo, Lim, Azman Osman, 2014 IEEE PES Innovative Smart Grid Technologies Conference (ISGT), pp.1-5, 2014-02, Institute of Electrical and Electronics Engineers (IEEE)
5 タイミング調整機構を持つ次世代データパス回路の遅延変動耐性と最適合成 / 金子, 峰雄, 科学研究費助成事業研究成果報告書, pp.1-6, 2013-06-03
6 遅延変動耐性を有する高信頼データパス回路の理論と最適合成に関する研究 / 金子, 峰雄, 科学研究費補助金研究成果報告書, pp.1-4, 2010-02-12
7 On the derivation of a minimum test set in high quality transition testing / Iwagaki, Tsuyoshi, Kaneko, Mineo, 10th Latin American Test Workshop, 2009. LATW '09., pp.1-6, 2009-03, Institute of Electrical and Electronics Engineers (IEEE)
8 Simultaneous Optimization of Skew and Control Step Assignments in RT-Datapath Synthesis / OBATA, Takayuki, KANEKO, Mineo, IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences, E91-A(12), pp.3585-3595, 2008-12-01, 電子情報通信学会
9 Safe clocking register assignment in datapath synthesis / Inoue, Keisuke, Kaneko, Mineo, Iwagaki, Tsuyoshi, IEEE International Conference on Computer Design, 2008. ICCD 2008, pp.120-127, 2008-10, Institute of Electrical and Electronics Engineers (IEEE)
10 Minimizing Minimum Delay Compensations for Timing Variation-Aware Datapath Synthesis / Inoue, Keisuke, Kaneko, Mineo, Iwagaki, Tsuyoshi, 51st Midwest Symposium on Circuits and Systems, 2008. MWSCAS 2008., pp.97-100, 2008-08, Institute of Electrical and Electronics Engineers (IEEE)
11 Concurrent skew and control step assignments in RT-level datapath synthesis / Obata, Takayuki, Kaneko, Mineo, ISCAS 2008. IEEE International Symposium on Circuits and Systems, 2008., pp.2018-2021, 2008-05, Institute of Electrical and Electronics Engineers (IEEE)
12 Novel Register Sharing in Datapath for Structural Robustness against Delay Variation / INOUE, Keisuke, KANEKO, Mineo, IWAGAKI, Tsuyoshi, IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences, E91-A(4), pp.1044-1053, 2008-04-01, 電子情報通信学会
13 極微細LSIのタイミング設計 : Timing Issues in Nanotechnology LSI / 金子, 峰雄, pp.1-24, 2007-03-07
14 Statistical Analysis Driven Synthesis of Application Specific Asynchronous Systems / OHASHI, Koji, KANEKO, Mineo, IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences, E90-A(3), pp.659-669, 2007-03-01, 電子情報通信学会
15 Characterization and Computation of Steiner Routing Based on Elmore's Delay Model / TAYU, Satoshi, KANEKO, Mineo, IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences, E85-A(12), pp.2764-2774, 2002-12-01, 電子情報通信学会
16 Assignment-Driven Loop Pipeline Scheduling and Its Application to Data-Path Synthesis / YOROZUYA, Toshiyuki, OHASHI, Koji, KANEKO, Mineo, IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences, E85-A(4), pp.819-826, 2002-04-01, 電子情報通信学会
17 Reliable Data Routing for Spatial-Temporal TMR Multiprocessor Systems / KANEKO, Mineo, IEICE TRANSACTIONS on Information and Systems, E84-D(12), pp.1790-1800, 2001-12-01, 電子情報通信学会

 


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